In the design of high-performance computer systems, power and temperature have become the dominant constraints. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance. On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems. Previous works have shown that the on-chip networks are expected to be one of the hottest spots of the chip. In our work, we focus on on-chip network temperature optimization. To achieve this, we first study the impact of the on-chip network traffic on the program execution, and then propose thermal-aware adaptive routing schemes for chip multiprocessors.;It is known that the execution of a program exhibits repetitive phases. Such property can be utilized to reduce the run time of architecture simulations. Conventionally, an application is examined in an architecture-independent manner to extract its phases. However, in the many-core system, as the communication structure of the application is becoming more important to the program execution, techniques that identify program phases without the consideration of the communication behavior of the application are becoming inadequate for CMPs. We propose to utilize communication behavior along with instruction behavior to determine phases of a multi-threaded application. The results reveal that the inclusion of the on-chip network traffic pattern can increase the accuracy of the phase detection significantly.;After the analysis of the impact of on-chip network on program execution, it is noticed that the traffic of the on-chip network is non-trivial. To resolve the thermal issues of the on-chip network, we explore the thermal-aware routing schemes. We delivered an integrated thermal modeling simulation framework. The operating temperature of the on-chip network is monitored, and packets are sent through paths that are "cooler". As a result, warmer routers are prevented from becoming hotspots. Several different thermal-aware routing schemes are presented. We evaluated both adaptive and deterministic routings, and they could be either minimal or non-minimal. Results show that our approaches can successfully reduce routers' peak temperature and thermal emergencies of the whole chip without causing any performance penalty.