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    Adaptive on-chip networks and their impact on processor architectures.

    机译:自适应片上网络及其对处理器体系结构的影响。

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    摘要

    In the design of high-performance computer systems, power and temperature have become the dominant constraints. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance. On-chip networks are becoming increasingly popular as a way to connect high-performance single-chip computer systems. Previous works have shown that the on-chip networks are expected to be one of the hottest spots of the chip. In our work, we focus on on-chip network temperature optimization. To achieve this, we first study the impact of the on-chip network traffic on the program execution, and then propose thermal-aware adaptive routing schemes for chip multiprocessors.;It is known that the execution of a program exhibits repetitive phases. Such property can be utilized to reduce the run time of architecture simulations. Conventionally, an application is examined in an architecture-independent manner to extract its phases. However, in the many-core system, as the communication structure of the application is becoming more important to the program execution, techniques that identify program phases without the consideration of the communication behavior of the application are becoming inadequate for CMPs. We propose to utilize communication behavior along with instruction behavior to determine phases of a multi-threaded application. The results reveal that the inclusion of the on-chip network traffic pattern can increase the accuracy of the phase detection significantly.;After the analysis of the impact of on-chip network on program execution, it is noticed that the traffic of the on-chip network is non-trivial. To resolve the thermal issues of the on-chip network, we explore the thermal-aware routing schemes. We delivered an integrated thermal modeling simulation framework. The operating temperature of the on-chip network is monitored, and packets are sent through paths that are "cooler". As a result, warmer routers are prevented from becoming hotspots. Several different thermal-aware routing schemes are presented. We evaluated both adaptive and deterministic routings, and they could be either minimal or non-minimal. Results show that our approaches can successfully reduce routers' peak temperature and thermal emergencies of the whole chip without causing any performance penalty.
    机译:在高性能计算机系统的设计中,功率和温度已成为主要限制因素。功耗增加会导致芯片温度升高,进而降低芯片的可靠性和性能。片上网络作为连接高性能单芯片计算机系统的一种方式正变得越来越流行。以前的工作表明,片上网络有望成为芯片上最热门的地方之一。在我们的工作中,我们专注于片上网络温度优化。为此,我们首先研究片上网络流量对程序执行的影响,然后提出针对芯片多处理器的热感知自适应路由方案。众所周知,程序的执行表现出重复的阶段??梢岳谜庵质粜岳醇跎偬逑到峁狗抡娴脑诵惺奔?。通常,以与体系结构无关的方式检查应用程序以提取其阶段。但是,在多核系统中,由于应用程序的通信结构对于程序执行变得越来越重要,因此在不考虑应用程序的通信行为的情况下识别程序阶段的技术对于CMP来说变得不足够。我们建议利用通信行为和指令行为来确定多线程应用程序的阶段。结果表明,包含片上网络流量模式可以显着提高相位检测的准确性。;在分析了片上网络对程序执行的影响后,发现芯片网络是不平凡的。为了解决片上网络的热问题,我们探索了热感知路由方案。我们提供了一个集成的热建模仿真框架。监控片上网络的工作温度,并通过“较冷”的路径发送数据包。结果,防止了温暖的路由器成为热点。介绍了几种不同的热感知路由方案。我们评估了自适应路由和确定性路由,它们可能是最小的也可能是非最小的。结果表明,我们的方法可以成功降低路由器的峰值温度和整个芯片的紧急情况,而不会造成任何性能损失。

    著录项

    • 作者

      Zhang, Yu.;

    • 作者单位

      Northwestern University.;

    • 授予单位 Northwestern University.;
    • 学科 Engineering, Computer.;Computer Science.
    • 学位 Ph.D.
    • 年度 2010
    • 页码 114 p.
    • 总页数 114
    • 原文格式 PDF
    • 正文语种 eng
    • 中图分类 ;
    • 原文服务方 国家工程技术数字图书馆
    • 关键词

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